Clock recovery technology is generally provided as a technology to recover a clock from a superimposed signal when the clock is superimposed on data. For example, according to high speed serial communication technology such as USB (Universal Serial Bus), a reception data is oversampled by using operation clock of frequency which is twice of data rate, so that clocks are restored.
On the other hand, for example, as shown in Gigabit Ethernet (a registered trademark) from 1000 BASE-T, when a receiver is configured by using a transceiver of a digital signal processing type including ADC (Analog to Digital Convertor), a circuit is configured so that an operation clock frequency corresponds to a data rate. That is, in a case of 1000 BASE-T, a communication process is implemented by 125 Msps, and the reception circuit operates by the clock signals of 125 MHz and an oversampling process is not performed generally. When a speed of the operational frequency of the ADC increases, a circuit configuration becomes complicated and a circuit area increases. To avoid this difficulty, the oversampling is not performed generally.
As a method estimating an optimum sampling position while performing the sampling processing by a frequency identical with the reception data, a technology called as Mueller-Muller Timing Recovery is known. Mueller-Muller Timing Recovery technology is the technology that estimates an optimum sampling timing corresponding to an interference wave caused by an inter-code interference. The technology adapts an algorithm that estimates the sampling position so as to satisfy a state that, as a sampling interval is made consonant with a period of the data rate, a main signal equals to amplitude of the interference wave that preceding or succeeding temporally.
On the other hand, the receiver for the digital signal processor includes an equalizer that is positioned a previous stage of a timing recovery part restoring the recovery clocks, and the equalizer eliminates the inter-code interference.